VLSI Architectures for Blind Equalization Based on Fractional-Order Statistics
نویسنده
چکیده
Four types of VLSI architectures for the hardware realization of the FLOS-CM algorithm are introduced in this paper. Each architecture is appropriate for a particular environment. The FLOS-CM algorithm is found to be amenable for implementation using logarithmic arithmetic. A logarithmic architecture is shown to require up to 50% less area and be 14% faster than a linear fixed-point arithmetic counterpart. In terms of AreaxTime and AreaxTime2 complexities, the logarithmic architecture is up to 120% better.
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